1. Field of The Invention
The present invention relates to a digital speedometer used for measuring and displaying the velocity of a moving member or the rotational speed of a rotating member. Specifically to a digital speedometer for automotive vehicles applicable to display vehicle speed on the basis of a counted value of pulses generated from a pulse generator in proportion to the rotational speed of a measured object, such as a rotating propeller or wheel of a vehicle.
2. Description of The Prior Art
Recently, there have been proposed and developed various digital speedometers which include pulse generators, pulse counters, indicator registers, visual display means, and timing pulse generators. In such digital speedometers for automotive vehicles, a pulse generator is engaged with a measured object, such as a vehicle wheel in such a manner so as to generate pulses in proportion to the vehicle speed. A pulse counter counts the number of pulses from the pulse generator for a predetermined constant time interval controlled by the timing pulse generator. The timing pulse generator also outputs a latch signal in response to which the counted value of pulses is shifted into the indicator register at a time just after completion of the pulse counting and thus the counted value is memorized in the indicator register. Subsequently, the counted value indicative of the vehicle speed is immediately displayed on the visual display.
In this manner, since the digital speedometer is controlled by a timing pulse generator in such a manner that the number of pulses is counted for a predetermined constant time interval by the pulse counter and the counted value is subsequently displayed on the visual display. When the measured object is kept at an essentially constant speed, the least significant digit of the displayed value flickers frequently on the display due to slight changes in speed, thereby having a distracting effect on a vehicle occupant monitoring the display. For example, if the vehicle speed is kept at 60.5 km/h, an intermediate value between 60 km/h and 61 km/h, the speedometer displays alternately either 60 km/h or 61 km/h, each for a relatively short time due to slight fluctuations in vehicle speed.
To avoid this, a prior art digital speedometer for automotive vehicles with a hysteresis processing circuit wherein the memorized value of the indicator register is renewed with the newly counted value from the pulse counter only when the absolute value of the difference between the newly counted value and the memorized value exceeds a predetermined threshold value, has been disclosed in Japanese Patent Second Publication (Tokko) Showa 60-29069.
This hysteresis processing circuit for a digital speedometer is shown in FIG. 1 and its operation is described with reference thereto:
A subtracter 13 generates an output signal c indicative of the difference between an output signal a, indicative of the actual vehicle speed according to a vehicle speed pulse counter 11, and an indicator signal b indicative of a memorized value from an indicator register 12. Then the output signal c from the subtracter 13 is input into the comparator 15. A digital setting circuit 14 wherein the hysteresis threshold value is set, also outputs a signal d indicative of the hysteresis value into the comparator 15. The comparator 15 compares the absolute value of the difference with the threshold value on the basis of the output signals c and d, and then the comparator 15 outputs a signal e into a logical multiply gate (AND gate) 16 only when the absolute value of the difference is greater than the above mentioned threshold value. Additionally, the AND gate receives a latch signal f generated from a timing pulse generator (not shown) at a time just after completion of each time cycle in which pulses are counted by the pulse counter 11. Therefore, when the latch signal 7 and the signal e are simultaneously input into the AND gate 16, the AND gate 16 is opened and as a result the counted value indicative of the actual vehicle speed is shifted from the pulse counter 11 to the indicator register 12 with the result that the memorized value of the register 12 is renewed.
As set forth above, the prior art hysteresis processing circuit for a digital speedometer for automotive vehicles requires a subtracter 13 and the comparator 15. In a vehicular digital speedometer, the visual display (not shown) must display a maximum vehicle speed of, for example, 200 km/h or more. Furthermore, the least significant digit of a displayed value and the resolution to which the vehicle speed is calculated is 1 km/h, as is generally known. For this reason, the subtracter 13 and the comparator 15 as well as the vehicle speed pulse counter 11 and the indicator register 12 must be of an 8 bit configuration or greater, thereby resulting in a relatively large digital circuit.
As described previously, if the least significant digit on the display and the resolution of the vehicle speed is 1 km/h, the hysteresis processing circuit 10 outputs signal e from the comparator 15 to the AND gate 16 only when the absolute value of the difference exceeds the threshold value of 1 km/h. That is to say, the absolute value must be greater than or equal to 2 km/h. As a result, the memorized value of the indicator register 12 is incremented or decremented by 2 km/h. In other words, the displayed value is changed in increments of .+-.2 km/h during acceleration or deceleration of the vehicle. In this construction, the performance required of a digital speedometer is not satisfied.
In order to overcome the above mentioned problem in the prior art digital speedometer with the hysteresis processing circuit, the resolution of the vehicle speed must be kept less than 1 km/h, for example 0.5 km/h. If the resolution of the vehicle speed and the threshold value of the setting circuit are set to 0.5 km/h and 1 km/h respectively, when the vehicle is gradually accelerated from 60 km/h, the counted value of the pulse counter 11 will be changed at the order of 60.5 km/h, 61 km/h, 61.5 km/h etc. . . . When the absolute value of the difference between the counted value of the pulse counter 11 and the memorized value of the indicator register 12 exceeds the threshold value of 1 km/h, that is to say, the counted value reaches to 61.5 km/h, the memorized value of 60 km/h is renewed with the counted value 61.5 km/h and then the display (not shown) displays 61 km/h because the least significant digit of the displayed value is incremented by 1 km/h.
In this manner, the displayed value of the digital speedometer 10 is incremented or decremented by 1 km/h during acceleration or deceleration. However, in prior art digital speedometers with a resolution of less than 1 km/h, a relatively large circuit construction is required for the pulse counter, subtracter, and comparator due to the increase in the number of digits computed by the pulse counter. In order to calculate vehicle speed at a higher resolution than 1 km/h, it is necessary that the number of pulses from the pulse generator be increased or that the time interval of the pulse counter be extended. However, an increase in the number of pulses results in a more expensive pulse generator. On the other hand, a longer time interval will decrease the responsiveness of the speedometer during acceleration and deceleration.